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LP1071 数据表(PDF) 7 Page - Freescale Semiconductor, Inc

部件名 LP1071
功能描述  802.11a/b/g Baseband System
PDF  32 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

LP1071 数据表(HTML) 7 Page - Freescale Semiconductor, Inc

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Functional Description
LP1071 Advance Information, Rev. 0.5
Freescale Semiconductor
7
PRELIMINARY
3.4
Analog Front End (AFE)
The Analog Front End (AFE) block consists of three Analog-to-Digital Converters (ADCs) and two
Digital-to-Analog Converters (DACs) as given in Table 2.
3.4.1
I/Q ADC
I/Q ADC specifications are shown in Table 3.
Table 2. AFE Components
Component
Description
Resolution
Clock
I/Q ADC
A 2-channel ADC whose digital output serves as input to digital baseband and
whose input is the differential signal from the RF (RX mode).
8-bit
22 Msps
I/Q DAC
A 2-channel DAC whose digital input is from baseband and output is a
differential signal for the RF (TX mode).
8-bit
44 Msps
RSSI ADC
A single ended, single channel ADC
6-bit
10 Msps
Auxiliary ADC
A single ended, single channel ADC
8-bit
1 Msps
Auxiliary DAC
A single ended, single channel DAC
8-bit
20 Msps
Table 3. I/Q ADC Specifications
Parameter
Condition
Min
Typ
Max
Units
Resolution
8
bit
Maximum Sampling Frequency
22
MHz
Signal Bandwidth
11
MHz
Input impedance
Fixed capacitance
Switched capacitance @Fs
1
1
pF
pF
Latency
4
cycles
Integral Nonlinearity (INL)
±1.0
LSB
Differential Nonlinearity (DNL)
± 0.5
LSB
Total Harmonic Distortion (THD)
Fin= 1MHz
Fin= 10MHz
–48.5
–47
dB
dB
SNR
Fin= 1MHz
Fin= 10MHz
48.5
47
dB
dB
ENOB
Fin= 1MHz
Fin= 10MHz
7.2
7.0
bit
bit
Channel-to-Channel mismatch
Gain
Phase
0.2
0.5
dB
Degree
DC offset after calibration
–1
+1
LSB
Wake-up time
From Shutdown
From Standby
1
10
ms
µs



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