ST72141K datasheet(127/132 Pages) STMICROELECTRONICS

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ST72141K

127/132

MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d)

Px.x/AINx

RAIN

VAIN

Cpin

5pF

VDD

VT = 0.6V

leakage

VT = 0.6V

Cpin

leakage

Chold

Sampling

Switch

RSS

at the pin due

to various junctions

Chold

6 pF

capacitance

= input capacitance

= threshold voltage

= sampling switch

= sample/hold

±1µA

VSS

= leakage current

ΚΩ

1 LSB (ideal)

1LSB

i deal

DDA

SSA

–

256

-----------------------------------------

Vin (LSBideal)

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(3) End point correlation line

TUE=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.

OE=Offset Error: deviation between the first actual

transition and the first ideal one.

GE=Gain Error: deviation between the last ideal

transition and the last actual one.

DLE=Differential Linearity Error: maximum devia-

tion between actual steps and the ideal one.

ILE=Integral Linearity Error: maximum deviation

between any actual transition and the end point

correlation line.

Digital Result ADCDR

255

254

253

123

456

253 254 255 256

(1)

(2)

TUE

DLE

ILE

(3)

VDDA

VSSA

ST72141K 数据表(PDF) 127 Page - STMicroelectronics

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