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ST72141K 数据表(PDF) 123 Page - STMicroelectronics |
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ST72141K 数据表(HTML) 123 Page - STMicroelectronics |
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123 / 132 page  ST72141K 123/132 MEMORY AND PERIPHERAL CHARACTERISTICS (Cont’d) Figure 65. SPI Master Timing Diagram CPHA=0, CPOL=0 2) Notes: 1) Data based on characterization results, not tested in production. 2) Measurement points are VOL, VOH, VIL and VIH in the SPI timing diagram SPI Serial Peripheral Interface Ref. Symbol Parameter Condition Value 1) Unit Min Max fSPI SPI frequency Master Slave 1/128 dc 1/4 1/2 fCPU 1tSPI SPI clock period Master Slave 4 2 tCPU 2tLead Enable lead time Slave 120 ns 3tLag Enable lag time Slave 120 ns 4tSPI_H Clock (SCK) high time Master Slave 100 90 ns 5tSPI_L Clock (SCK) low time Master Slave 100 90 ns 6tSU Data set-up time Master Slave 100 100 ns 7tH Data hold time (inputs) Master Slave 100 100 ns 8tA Access time (time to data active from high impedance state) Slave 0 120 ns 9tDis Disable time (hold time to high im- pedance state) 240 ns 10 tV Data valid Master (before capture edge) Slave (after enable edge) 0.25 120 tCPU ns 11 tHold Data hold time (outputs) Master (before capture edge) Slave (after enable edge) 0.25 0 tCPU ns 12 tRise Rise time (20% VDD to 70% VDD, CL = 200pF) Outputs: SCK,MOSI,MISO Inputs: SCK,MOSI,MISO,SS 100 100 ns µs 13 tFall Fall time (70% VDD to 20% VDD, CL = 200pF) Outputs: SCK,MOSI,MISO Inputs: SCK,MOSI,MISO,SS 100 100 ns µs 1 6 7 10 11 12 13 SS (INPUT) SCK (OUTPUT) MISO MOSI (INPUT) (OUTPUT) 4 5 D7-OUT D6-OUT D0-OUT D7-IN D6-IN D0-IN VR000109 |
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