ST72411R datasheet(36/71 Pages) STMICROELECTRONICS

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ST72411R

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8-BIT TIMER (Cont’d)

5.3.4 Functional description

5.3.4.1 8-bit counting and interrupt capability

on counter underflow

Whatever the division factor defined for the pres-

caler, the Timer Counter works as an 8-bit down-

counter. The input clock frequency is user selecta-

ble using the PS0 and PS1 bits.

When the downcounter underflows (transition from

00h to FFh), the UDF (Timer Underflow) bit in the

TSCR is set. If the ETI (Enable Timer Interrupt) bit

in the TSCR is also set, an interrupt request is

generated.

The Timer interrupt can be used to exit the MCU

from WAIT or HALT mode.

The TCR can be written at any time by software to

define a time period ending with a UDF event, and

therefore manage delay or timer functions.

UDF is set when the counter underflows (clock

pulse creating the transition from 00h to FFh);

however, it may also be set by setting bit 4 of the

TSCR register. The UDF bit must be cleared by

user software when servicing the timer interrupt to

avoid undesired interrupts when leaving the inter-

rupt service routine. After reset, the 8-bit counter

caler is loaded with 1FFh, and the TSCR register

is loaded with 050h. This means that the Timer is

stopped (PSE=“0”) and the timer interrupt is disa-

bled.

Note: A write to the TCR register will predominate

over the 8-bit counter decrement to 00h function,

i.e. if a write and a TCR register decrement to 00h

occur simultaneously, the write will take prece-

dence, and the UDF bit is not set until the 8-bit

counter underflows again.

Application Notes

– A time base interrupt can be created by using the

UDF interrupt to generate interrupts at regular

time intervals.

With the maximum prescaler ratio set, the maxi-

mum period between two UDF flags is:

512/fTIMER

If we consider the previous example:

(fTIMER=fCPU/16)

we have

(512*16) / fCPU

(2.3 ms for a fCPU of 3.58MHz).

With the minimum prescaler ratio set, the mini-

mum step of the 8-bit downcounter, i.e the res-

olution, is 1/fTIMER, that means 16 / fCPU (4.5 µs

for a fCPU=3.58MHz).

– When the maximum division factor (512) is set,

the input clock to the 8-bit downcounter is the 9th

and last bit of the prescaler. This means, the 9-

bit prescaler and the 8-bit counter are serialized

and can be considered as a 16-bit counter with a

frequency of fTIMER/512.

5.3.4.2 Gated mode

(TOUT = “0”, DOUT = “1”)

Figure 25. fTIMER Clock in Gated Mode

In this mode, the prescaler is decremented by the

Timer clock input, but only when the signal on the

TIMIO pin is held high (fCPU/16 gated by TIMIO).

See Figure 39 and Figure 40.

This mode is selected by clearing the TOUT bit in

the TSCR register (i.e. as input) and setting the

DOUT bit.

Figure 26. .Gated Mode Operation

fTIMER

TIMIO

fCPU/16

fEXT

xx1

Counter Value

TIMIO Pin

Timer Clock

Value 1

Value 2

Pulse Length

xx2

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