ST72411R datasheet(41/71 Pages) STMICROELECTRONICS

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ST72411R

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LCD DRIVER (Cont’d)

5.4.2 Segment and Common signals

Each picture element of the LCD panel is turned

on when the differential voltage between the seg-

ment signal and the common signal rises above a

certain threshold voltage. It is turned off when the

voltage is below the threshold voltage.

Common signals determine the select timing with-

in a frame cycle. The common signals have identi-

cal waveforms, but different phases. Each com-

mon signal has the highest amplitude only in the

corresponding phase of a frame cycle. At the other

phases, the signal amplitude is lower (2/3 - 1/3). A

picture element can only be turned on with high

signal amplitude.

The LCD driver has 32x4 bits of display memory.

The corresponding address locations are read out

automatically in synchronisation with the select

timing of COM0, COM1, COM2 and COM3.

Figure 32. Waveforms of LCD Outputs

5.4.3 Reference Voltages

The display voltage levels are supplied by an inter-

nal resistor divider network as shown in Figure 47

This LCD driver generates 4 reference voltages

from VSS and VDD through an internal RC divider

network.

In order to increase current during transitions and

to reduce consumption in static state, two resistive

networks are used. The high resistive divider is

permanently switched on during the LCD opera-

tion. The low resistive divider is only switched on

for a short period of time when the levels of com-

mon and segment lines change. This method com-

bines low source impedance for fast switching of

the LCD with high source impedance for low pow-

er consumption. When the LCD is disabled (bit

LCDEN=0), the internal resitive network is also

switched off for minimum power consumption.

Figure 33. LCD Reference Voltage generation

5.4.4 Display Example

The example in Figure 48 shows a sequence of

two identical frames containing the waveforms dis-

playing a “4” in a seven-segment display.

In each TFRAME period, the LCD driver automati-

cally switches on each of the four COM signals for

one TLCD period. COM0 is on in the first period,

COM1 in the second period and so on. To switch

them on, the waveform goes above and below the

threshold voltages. When the waveform is within

the thresholds, the COM is off.

The SEG signals are controlled by software by

programming the display memory.

– SEG 0 is off during the first period and on for the

remaining three periods.

– SEG 1 is off during TLCD periods 1, 2, and 4 and

on for TLCD period 3.

To program the display memory for this example,

software must write 00h in locations 0140h -0143h

and 01h in locations 144h through 0147h (refer to

Section 5.4.7)

VDD

2/3

1/3

GND

COM ON

LCD clock

COMi

COM OFF

VDD

2/3

1/3

GND

SEG ON

SEGi

SEG OFF

2VDD/3

VDD

VSS

RL ON

LCDE

VDD

VSS

VDD/3

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