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ST90158 - SERIAL PERIPHERAL INTERFACE (SPI)

SERIAL PERIPHERAL INTERFACE (Cont’d)

9.4.3 Functional Description

The SPI, when enabled, receives input data from

the internal data bus to the SPI Data Register

(SPIDR). A Serial Clock (SCK) is generated by

controlling through software two bits in the SPI

Control Register (SPICR). The data is parallel

loaded into the 8 bit shift register during a write cy-

cle. This is shifted out serially via the SDO pin,

MSB first, to the slave device, which responds by

sending its data to the master device via the SDI

pin. This implies full duplex transmission if 3 I/O

pins are used with both the data-out and data-in

synchronized with the same clock signal, SCK.

Thus the transmitted byte is replaced by the re-

ceived byte, eliminating the need for separate “Tx

empty” and “Rx full” status bits.

When the shift register is loaded, data is parallel

transferred to the read buffer and becomes availa-

ble to the CPU during a subsequent read cycle.

The SPI requires three I/O port pins:

SCK

Serial Clock signal

SDO

Serial Data Out

SDI

Serial Data In

An additional I/O port output bit may be used as a

slave chip select signal. Data and Clock pins I C

Bus protocol are open-drain to allow arbitration

and multiplexing.

Figure 65 below shows a typical SPI network.

Figure 65. A Typical SPI Network

9.4.3.1 Input Signal Description

Serial Data In (SDI)

Data is transferred serially from a slave to a mas-

ter on this line, most significant bit first. In an S-

BUS/I

2C-bus configuration, the SDI line senses

the value forced on the data line (by SDO or by an-

other peripheral connected to the S-bus/I2C-bus).

9.4.3.2 Output Signal Description

Serial Data Out (SDO)

The SDO pin is configured as an output for the

master device. This is obtained by programming

the corresponding I/O pin as an output alternate

function. Data is transferred serially from a master

to a slave on SDO, most significant bit first. The

master device always allows data to be applied on

the SDO line one half cycle before the clock edge,

in order to latch the data for the slave device. The

SDO pin is forced to high impedance when the SPI

is disabled.

During an S-Bus or I2C-Bus protocol, when arbi-

tration is lost, SDO is set to one (thus not driving

the line, as SDO is configured as an open drain).

Master Serial Clock (SCK)

The master device uses SCK to latch the incoming

data on the SDI line. This pin is forced to a high im-

pedance state when SPI is disabled (SPEN,

SPICR.7 = “0”), in order to avoid clock contention

from different masters in a multi-master system.

The master device generates the SCK clock from

INTCLK. The SCK clock is used to synchronize

data transfer, both in to and out of the device,

through its SDI and SDO pins. The SCK clock

type, and its relationship with data is controlled by

the CPOL (Clock Polarity) and CPHA (Clock

Phase) bits in the Serial Peripheral Control Regis-

ter (SPICR). This input is provided with a digital fil-

ter which eliminates spikes lasting less than one

INTCLK period.

Two bits, SPR1 and SPR0, in the Serial Peripheral

Control Register (SPICR), select the clock rate.

Four frequencies can be selected, two in the high

frequency range (mostly used with the SPI proto-

col) and two in the medium frequency range

(mostly used with more complex protocols).

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