ST90135 datasheet(136/190 Pages) STMICROELECTRONICS

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ST90158 - SERIAL PERIPHERAL INTERFACE (SPI)

SERIAL PERIPHERAL INTERFACE (Cont’d)

The data on the SDA line is sampled on the low to

high transition of the SCL line.

SPI working with an I2C-bus

To use the SPI with the I2C-bus protocol, the SCK

line is used as SCL; the SDI and SDO lines, exter-

nally wire-ORed, are used as SDA. All output pins

must be configured as open drain (see Figure 67).

Figure 26 illustrates the typical I2C-bus sequence,

comprising 5 phases: Initialization, Start, Trans-

mission, Acknowledge and Stop. It should be not-

ed that only the first 8 bits are handled by the SPI

peripheral; the ACKNOWLEDGE bit must be man-

aged by software, by polling or forcing the SCL

and SDO lines via the corresponding I/O port bits.

During the transmission phase, the following I2C-

bus features are also supported by hardware.

Clock Synchronization

In a multimaster I2C-bus system, when several

masters generate their own clock, synchronization

is required. The first master which releases the

SCL line stops internal counting, restarting only

when the SCL line goes high (released by all the

other masters). In this manner, devices using dif-

ferent clock sources and different frequencies can

be interfaced.

Arbitration Lost

When several masters are sending data on the

SDA line, the following takes place: if the transmit-

ter sends a “1” and the SDA line is forced low by

another device, the ARB flag (SPICR.5) is set and

the SDO buffer is disabled (ARB is reset and the

SDO buffer is enabled when SPIDR is written to

again). When BMS is set, the peripheral clock is

supplied through the INT2 line by the external

clock line (SCL). Due to potential noise spikes

(which must last longer than one INTCLK period to

be detected), RX or TX may gain a clock pulse.

Referring to Figure 69, if device ST9-1 detects a

noise spike and therefore gains a clock pulse, it

will stop its transmission early and hold the clock

line low, causing device ST9-2 to freeze on the 7th

bit. To exit and recover from this condition, the

BMS bit must be reset; this will cause the SPI logic

to be reset, thus aborting the current transmission.

An End of Transmission interrupt is generated fol-

lowing this reset sequence.

Figure 69. SPI Arbitration

INTERNAL SERIAL

CLOCK

BHS

ST9-1

SCK

MSPI

LOGIC

CONTROL

INT 2

MSPI

CONTROL

LOGIC

BHS

SCK

INTERNAL SERIAL

CLOCK

ST9-2

INT 2

345

ST9-2-SCK

ST9-1-SCK

SPIKE

VR001410

ST90135 数据表(PDF) 136 Page - STMicroelectronics

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