ST90135 datasheet(139/190 Pages) STMICROELECTRONICS

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ST90158 - SERIAL PERIPHERAL INTERFACE (SPI)

SERIAL PERIPHERAL INTERFACE (Cont’d)

9.4.9 Register Description

It is possible to have up to 3 independent SPIs in

the same device (refer to the device block dia-

gram). In this case they are named SPI0 thru

SPI2. If the device has one SPI converter it uses

the register adresses of SPI0. The register map is

the following:

Note: In the register description on the following

pages, register and page numbers are given using

the example of SPI0.

SPI DATA REGISTER (SPIDR)

R253 - Read/Write

Reset Value: undefined

Bit 7:0 = D[0:7]:

SPI Data.

This register contains the data transmitted and re-

ceived by the SPI. Data is transmitted bit 7 first,

and incoming data is received into bit 0. Transmis-

sion is started by writing to this register.

Note: SPIDR state remains undefined until the

end of transmission of the first byte.

SPI CONTROL REGISTER (SPICR)

R254 - Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = SPEN:

Serial Peripheral Enable.

0: SCK and SDO are kept tristate.

1: Both alternate functions SCK and SDO are ena-

bled.

Note: furthermore, SPEN (together with the BMS

bit) affects the selection of the source for interrupt

channel B0. Transmission starts when data is writ-

ten to the SPIDR Register.

Bit 6 = BMS:

S-bus/I2C-bus Mode Selector.

0: Perform a re-initialisation of the SPI logic, thus

allowing recovery procedures after a RX/TX fail-

ure.

1: Enable S-bus/I2C-bus arbitration, clock synchro-

nization and Start/ Stop detection (SPI used in

an S-bus/I2C-bus protocol).

Note: when the BMS bit is reset, it affects (togeth-

er with the SPEN bit) the selection of the source

for interrupt channel B0.

Bit 5 = ARB:

Arbitration flag bit.

This bit is set by hardware and can be reset by

software.

0: S-bus/I2C-bus stop condition is detected.

1: Arbitration lost by the SPI in S-bus/I2C-bus

mode.

Note: when ARB is set automatically, the SDO pin

is set to a high value until a write instruction on

SPIDR is performed.

Bit 4 = BUSY:

SPI Busy Flag.

This bit is set by hardware. It allows the user to

monitor the SPI status by polling its value.

0: No transmission in progress.

1: Transmission in progress.

Bit 3 = CPOL:

Transmission Clock Polarity.

CPOL controls the normal or steady state value of

the clock when data is

not being transferred.

Please refer to the following table and to Figure 74

to see this bit action (together with the CPHA bit).

Note: As the SCK line is held in a high impedance

state when the SPI is disabled (SPEN = “0”), the

SCK pin must be connected to VSS or to VCC

through a resistor, depending on the CPOL state.

Polarity should be set during the initialisation rou-

tine, in accordance with the setting of all peripher-

als, and should not be changed during program

execution.

SPIn

Page

SPIDR R253

SPI0

SPICR R254

SPI0

SPIDR1 R253

SPI1

SPICR1 R254

SPI1

SPIDR2 R245

SPI2

SPICR2 R246

SPI2

SPEN

BMS

ARB

BUSY

CPOL

CPHA

SPR1

SPR0

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