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STA014 数据表(PDF) 12 Page - STMicroelectronics |
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STA014 数据表(HTML) 12 Page - STMicroelectronics |
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12 / 45 page  5 - I 2C BUS SPECIFICATION The STA014 supports the I 2C protocol. This pro- tocol defines any device that sends data on to the bus as a transmitter and any device that reads the data as a receiver. The device that controls the data transfer is known as the master and the others as the slave. The master always starts the transfer and provides the serial clock for synchro- nisation. The STA014 is always a slave device in all its communications. 5. 1 - COMMUNICATION PROTOCOL 5.1.0 - Data transition or change Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while the clock is high are used to identify START or STOP condition. 5.1.1 - Start condition START is identified by a high to low transition of the data bus SDA signal while the clock signal SCL is stable in the high state. A START condition must precede any command for data transfer. The following 4 figures (fig. 12, 13, 14, 15) show the available connection diagrams as far as ADPCM encoding function. As shown in the fig- ures some configuration is not available in SO28 package. SDI GPSO_REQ GPSO_SCKR GPSO_DATA SCKR LRCKT SCKT SDO OCLK DATA_REQ MCU DAC BIT_EN I2C D99AU1122A TQFP44 LFBGA64 Figure 14. Input from BITSTREAM, Output from GPSO DATA_REQ DATA_REQ LRCK_ADC SDI_ADC SDO LRCKT SCKT SCK_ADC SDI_ADC I2C I2C OCLK MCU ADC SLAVE MCU ADC MASTER DAC DAC D99AU1123A OCLK SDO SCKT LRCKT SO28 TQFP44 LFBGA64 SO28 TQFP44 LFBGA64 Figure 13. Input from ADC, Output from I2C + IRQ GPSO_SCKR GPSO_REQ LRCK_ADC SCK_ADC SDI_ADC GPSO_DATA MCU ADC MASTER DAC D99AU1124A OCLK SDO SCKT LRCKT TQFP44 LFBGA64 Figure 15. Input from ADC, Output from GPSO SDI SCKR LRCKT SCKT SDO OCLK DATA_REQ MCU DAC BIT_EN I2C D99AU1121A SO28 TQFP44 LFBGA64 Figure 12. Input from BITSTREAM, Output from I2C STA013 compatible mode STA014-STA014B-STA014T 12/45 |
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