STA014 datasheet(32/45 Pages) STMICROELECTRONICS

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GPSO_CONF

Address: 0xBA (186)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

XXXXXX

GRP

GSP

GSP:

GPSO clock polarity

Using this bit the GPSO_SCKR polarity can

be controlled. Clearing GSP bit data on

GPSO_DATA line will be provided on the

rising edge of GPSO_SCKR (sampling on

falling edge). Setting GSP bit data are

provided on falling edge of GPSO_SCKR

(sampling on rising edge)

GRP:

GPSO Request Polarity

This bit is used to determine the polarity of

GPSO_REQ signal. If GRP bit is cleared

data are valid on GPSO_REQ signal high. If

this bit is set data are valid on GPSO_REQ

signal low

ADC_ENABLE

Address: 0xBB (187)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

XXXX

XXX

ADCEN

This register controls if the ADPCM data to be

encoded comes from A/D interface or from MP3

bitstream input interface.

If ADCEN bit is set data to be encoded comes

from ADC interface, otherwise data comes from

MP3 stream interface

ADC_CONF

Address: 0xBC (188)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

ALRCS ALRCP ASCP ADC AIIS

Using this register the ADC input interface can be

configured as follow:

AIIS:

ADC I2S mode

0 =

sample word must be aligned with

LRCK (no I

2S mode)

1 =

sample word not aligned with LRCK

2S compliant mode)

ADC:

ADC Data Config.

0 =

sample word is LSB first

1 =

sample word is MSB first

ASCP:

ADC Serial Clock Polarity

0 =

Data is sampled on rising edge

1 =

Data is sampled an falling edge

ALRCP:

ADC Left/Right Clock Polarity

ALRCS:

ADC Left/Right Clock Start value. This two

bits permit to determine Left/Right clock

usage according to the following table:

ALRCP

ALRCS

LEFT/RIGHT COUPLE

(Data1, Data2)

(Data3, Data4)

(0, 1)

(2, 3)

(0, 1)

(2, 3)

(1, 2)

(3, 4)

DATA 0

LRCK

DATA

DATA 1

DATA 2

DATA 3

DATA 4

D99AU1065

STA014-STA014B-STA014T

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