STA014 datasheet(26/45 Pages) STMICROELECTRONICS

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MFSDF (X)

Address: 0x61 (97)

Type: R/W

Software Reset: 0x07

Hardware Reset: 0x07

MSB

LSB

M3M2M1M0

The register contains the values for PLL X divider

(see Fig. 7).

The value is changed by the internal STA014

Core, to set the clocks frequencies, according to

the incoming bitstream. This value can be even

set by the user to select the PCM interface con-

figuration.

The VCO output frequency is divided by (X+1).

This register is a reference for 32KHz and 48 KHz

input bitstream.

DAC_CLK_MODE (99)

Address: 0x63

Type: RW

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

XXXXX

MODE

This register is used to select the operating mode

for OCLK clock signal. If it is set to ’1’, the OCLK

frequency is fixed, and it is mantained to the

value fixed by the user even if the sampling fre-

quency of the incoming bitstream changes. It the

MODE flag is set to ’0’, the OCLK frequency

changes, and can be set to (512, 384, 256) * Fs.

The default configuration for this mode is 256 *

Fs. When this mode is selected, the default

OCLK frequency is 12.288 MHz.

PLLFRAC_L ([7:0])

MSB

LSB

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

PLLFRAC_H ([15:8])

MSB

LSB

PF15 PF14 PF13 PF12 PF11 PF10

PF9

PF8

Address: 0x64 - 0x65 (100 - 101)

Type: R/W

Software Reset: 0x46 | 0x5B

Hardware Reset: 0xNA | 0x5B

The registers are considered logically concate-

nated and contain the fractional values for the

PLL, used to select the internal configuration.

After Reset, the values are NA, and the opera-

tional setting are done when the MPEG synchro-

nisation is achieved.

The following formula describes the relationships

among all the STA014 fractional PLL parameters:

OCLK_Freq

= 



+ 1







⋅ 



MCLK_freq

+ 1







⋅ 



+ 1 +

FRAC

65536







where:

FRAC=256 x FRAC_H + FRAC_L (decimal)

These registers are a reference for 48 / 24 / 12 /

32 / 16 / 8KHz audio.

PCMCROSS

Address: 0x56 (86)

Type: R/W

Software Reset: 0x00

Hardware Reset: 0x00

MSB

LSB

Description

Left channel is mapped on the left output.

Right channel is mapped on the Right output

Left channel is duplicated on both Output channels.

Right channel is duplicated on both Output channels

Right and Left channels are toggled

The default configuration for this register is ’0x00’.

STA014-STA014B-STA014T

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