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数据搜索系统，热门电子元器件搜索 |
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STA014 数据表(PDF) 23 Page - STMicroelectronics |
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STA014 数据表(HTML) 23 Page - STMicroelectronics |
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23 / 45 page  ADPCM_DATA_READY Address: 0x52 (82) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 XX XXXXX ADR ADR: Adpcm Data Ready This bit signal ADPCM encoded data are ready to be retrieved. PLLFRAC_441_H Address: 0x52 (82) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 PF15 PF14 PF13 PF12 PF11 PF10 PF9 PF8 The registers are considered logically concate- nated and contain the fractional values for the PLL, for 44.1KHz reference frequency. (see also PLLFRAC_L and PLLFRAC_H regis- ters) ADPCM_SAMPLE_FREQ Address: 0x53 (83) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 X X X ADPCM_SF ADPCM_SF: Adpcm Sample Frequency 0x02 8KHz 0x0A 16KHz 0x0E 32KHz PCMDIVIDER Address: 0x54 (84) Type: RW Software Reset: 0x01 Hardware Reset: 0x01 765 432 10 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PCMDIVIDER is used to set the frequency ratio between the OCLK (Oversampling Clock for DACs), and the SCKT (Serial Audio Transmitter Clock). The relation is the following: SCKT_freq = OCLK_freq 2 (1 + PCM_DIV) STA014-STA014B-STA014T 23/45 |
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