T80C5112-RKFEV datasheet(16/97 Pages) ATMEL

16 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

Figure 3. Reset sources

Notes: RST pin available only on 48 and 52 pins versions.

Notes: RST pin available only on LPC versions.

7.3. Power-On Reset

The T80C5112 has a power on reset (POR) module which reset the chip during the initial power raise. The internal

power on reset pulse duration is 24 clock periods of the CPU clock. The chip can also be reseted by the P3.6/

RST/Vpp pin provided the EXT_RST bit of the configuration byte is high.

This module set the POF bit vhen Vcc is below the memory data retention voltage.

The behavior or POR and PFD is shown on Figure 4.

7.4. Power-Fail Detector

The Power-Fail Detector (PFD) is controlled by RSTD bit in PCON register. The PFD is disabled upon reset.

When enabled, the power supply is continuously monitored and an internal reset is generated(1) if VDD goes

below VRST for at least 60 ns.

If the power supply rises again over VRST+(

2), the internal reset completes after 24 CPU clock periods.

If RSTD is reset, the power supply monitoring is disabled.

RST_EXT

Reset

RST pin*

CONF

CPU Clock

+24 Ck

Hardware WD

POR

PCA WD

RST pin*

PFD

Fail

RSTD

PCON

POF

PCON

set

T80C5112-RKFEV 数据表(PDF) 16 Page - ATMEL Corporation

T80C5112-RKFEV 数据表(HTML) 16 Page - ATMEL Corporation

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