T80C5112-RKFEV datasheet(47/97 Pages) ATMEL

47 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

Reset Value= 00010100b

12.4.5.2. Serial Peripheral STAtus register (SPSTA)

The

Serial Peripheral Status Register contains flags to signal the following conditions:

Data transfer complete

Write collision

Inconsistent logic level on SS pin (mode fault error)

Table 24 describes the SPSTA register and explains the use of every bit in the register:

Reset Value= 00X0XXXXb

Table 24. Serial Peripheral Status and Control register

SPR1

Serial Peripheral Rate (SPR2:SPR1:SPR0)

000 : FCLK PERIPH /2

001 : FCLK PERIPH /4

010 : FCLK PERIPH /8

011 : FCLK PERIPH /16

SPR0

100 : FCLK PERIPH /32

101 : FCLK PERIPH /64

110 : FCLK PERIPH /128

111 : External clock, output of BRG

SPIF

WCOL

MODF

Bit

Number

Bit Mnemonic

R/W

Mode

Description

SPIF

Serial Peripheral data transfer flag

Clear by hardware to indicate data transfer is in progress or has been approved by a clearing

sequence.

Set by hardware to indicate that the data transfer has been completed.

WCOL

Write Collision flag

Cleared by hardware to indicate that no collision has occurred or has been approved by a

clearing sequence.

Set by hardware to indicate that a collision has been detected.

Reserved

The value read from this bit is indeterminate. Do not set this bit

MODF

Mode Fault

Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been

approved by a clearing sequence.

Set by hardware to indicate that the SS pin is at inappropriate logic level

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Bit

Number

Bit Mnemonic

R/W

Mode

Description

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