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T80C5112-RKFEV 数据表(PDF) 37 Page - ATMEL Corporation

部件名 T80C5112-RKFEV
功能描述  8-bit Microcontroller with A/D converter
PDF  97 Pages
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制造商  ATMEL [ATMEL Corporation]
网页  http://www.atmel.com
标志 ATMEL - ATMEL Corporation

T80C5112-RKFEV 数据表(HTML) 37 Page - ATMEL Corporation

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Rev. B - November 10, 2000
37
Preliminary
T80C5112
Table 18. SCON Register
SCON - Serial Control Register for UART (98h)
Reset Value = 0000 0000b
Bit addressable
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit Number
Bit
Mnemonic
Description
7
FE
Framing Error bit (SMOD0=1) for UART
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
SM0
Serial port Mode bit 0 (SMOD0=0) for UART
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
6
SM1
Serial port Mode bit 1 for UART
SM0
SM1
ModeDescriptionBaud Rate
0
0
0Shift RegisterFXTAL/12 (FXTAL/6 X2 mode)
0
1
18-bit UARTVariable
1
0
29-bit UARTFXTAL/64 or FXTAL/32 (FXTAL/32 or FXTAL/16 X2 mode)
1
1
39-bit UARTVariable
5
SM2
Serial port Mode 2 bit / Multiprocessor Communication Enable bit for UART
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit
should be cleared in mode 0.
4
REN
Reception Enable bit for UART
Clear to disable serial reception.
Set to enable serial reception.
3
TB8
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 for UART.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2
RB8
Receiver Bit 8 / Ninth bit received in modes 2 and 3 for UART
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1
TI
Transmit Interrupt flag for UART
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.
0
RI
Receive Interrupt flag for UART
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 11. and Figure 12. in the other modes.



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