T80C5112-RKFEV datasheet(42/97 Pages) ATMEL

42 / 97 page

Rev. B - November 10, 2000

Preliminary

T80C5112

12.4. Functional Description

Figure 16 shows a detailed structure of the SPI module.

Figure 16. SPI Module Block Diagram

12.4.1. Operating Modes

The Serial Peripheral Interface can be configured as one of the two modes: Master mode or Salve mode. The

configuration and initialization of the SPI module is made through one register:

The Serial Peripheral CONtrol register (SPCON)

Once the SPI is configured, the data exchange is made using:

SPCON

The Serial Peripheral STAtus register (SPSTA)

The Serial Peripheral DATa register (SPDAT)

During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially).

A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A

Slave Select line (SS) allows individual selection of a Slave SPI device; Slave devices that are not selected do not

interfere with SPI bus activities.

When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending

data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in

synchronized with the same clock (Figure 17).

Shift Register

Internal Bus

Control

Logic

MISO

MOSI

SCK

Clock

Logic

Clock

Divider

Clock

Select

/64

/128

SPI Interrupt Request

8-bit bus

1-bit signal

IntClk

/32

/16

Receive Data Register

SPDAT

SPI

Control

SPSTA

CPHA

SPR0

SPR1

CPOL

MSTR

SSDIS

SPEN

SPR2

SPCON

WCOL

MODF

SPIF

---

External Clk

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