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STLC1511

3.3 TRANSMIT PATH SPECIFICATIONS

<19>Minimum DS frequency is 36*4.3125kHz=155.25kHz and as such the coupling capacitors between RXINP/N and RXDCIP/N

must be such that the high pass pole is ~15kHz (typical). With a 1kW minimum input impedance at RXDCIP/N this gives a capacitor

value of about 10nF. This gives a 1t settling time of 10ms.To guarantee 12-bit performance a minimum of 10t settling gives 100ms.

<20>Minimum DS frequency is 7*4.3125kHz=30.1875kHz and as such the coupling capacitors between RXINP/N and RXDCIP/N

must be such that the high pass pole is ~3kHz (typical). With a 1kW minimum input impedance at RXDCIP/N this gives a capacitor

value of about 53nF. This gives a 1t settling time of 53ms.To guarantee 12-bit performance a minimum of 10t settling gives 530ms.

Table 3. Transmit Path Specifications

Description

min

typ

max

Units

Comments

0 =< D =< 16

D > 16

-(2 · D) - 1.8

-33.8

-(2 · D)

-32.0

-(2 · D) - 1.0

-31.0

dB

Where “D” is the binary

value in b[11:7] of the

control word.

Includes Vcc,

temperature, process,

and frequency variation.

Gain Step Size

1.8

2.0

2.2

dB

For a 1 LSB change in

the control word at a

fixed frequency f (30kHz

=< f =< 540kHz)

(relative to ideal gain of 2dB per

step.)

-0.4

+0.4

dB

For more than a 1LSB

change in the control

word.

Assumes a fixed Vcc,

temperature, and

frequency.

-0.3

0.3

dB

For a fixed Vcc and

frequency f (30kHz =< f

=< 540kHz) relative to

Gain Variation with Supply

-0.1

0.1

dB

For a fixed frequency f.

(30kHz =< f =< 540kHz)

and fixed temperature

relative to Vcc=5.0V.

30kHz =< f =< 120kHz

155kHz =< f =< 540kHz

-0.6

-1.0

0

0

dB

For a fixed Vcc and

temperature.

relative to 30kHz

relative to 155kHz