STLC1511 datasheet(20/31 Pages) STMICROELECTRONICS

20 / 31 page

STLC1511

20/31

Figure 10. Clip Indicator Output.

Bit 0 in the “AFE Status” register is also set to high

when a clip occurs. This bit can be disabled via the

control interface, see Table 8 on page 21 for more

details. This bit is cleared on read. For more informa-

tion see "Digital Interface And Memory Map" on page

20.

3.6.2 Tx Loop Back

When bit “b1” of register “011” (AFE Control 4) is as-

serted the data received on the TXSIN[1:0] pins is

converted to parallel and then sent directly to both the

DAC and the RX parallel data input replacing the usu-

al data from the ADC.

This allows a “loop back” to the input TX data from

TXSIN[1:0] to the RXSOUT[1:0] to help the testability

of the serial interface.

3.7 Digital Interface And Memory Map

All parametric specifications in Table 2 on page 6

and Table 3 on page 9 are guaranteed assuming that

the Digital Interface is inactive.

All parametric specifications in Table 2 and Table 3

are guaranteed assuming that the Digital Interface is

inactive. The digital interface operates at a rate of

35.328 MHz. The companion DSP chip, STLC1510,

sources the 35.328 MHz clock used by the AFE. To

minimize the impact of digital noise on the

STLC1511, this supplied clock is gated, and is only

enabled during data transfers and during reset. The

clock does not need to be present in order to re-

set the chip.

The processor interface consists of four pins: 1) the

35.328 MHz gated clock (DIGCLK); 2) a data in port

for data transfers (DRX); a data out pin for data trans-

fer (DTX); and 4) a chip select pin (ENB).

There are a total of 12 bits which are serially transmit-

ted between the STLC1510 and AFE during data

transfers. The gated clock lasts for a duration of 12

clock cycles. This 12 cycle interaction consists of a R/

W bit, a 3 bit address, and a 8 bit data word.

The format for this serial transaction is given below in

Figure 11.

C K 35M

FRM C L K

RX SO U T[0]

RX SO U T[1]

b[15:8]= 7F

b[7:0]= F F

RXSO U T [0]

RXSO U T [1]

b[15:8]= 80

b[7:0]= 00

P o sitive C lip

Nega tive C lip

Figure 11. Digital Interface Timing Diagram

DIGCK

ENB

(35MHz)

DATA[b7:b0] for write access

ADDRESS

R/W

DRX

[a2:a0]

DATA[b7:b0] for read access

DTX

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