STLC1511 datasheet(19/31 Pages) STMICROELECTRONICS

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STLC1511

Figure 9. Serial Interface Block Diagram

3.6.1 ADC Clip Indicator

Normally, the receive signal level is set such that the

input to the STLC1511 plus the RxPGA gain will not

saturate the input to the ADC converter (for maxi-

mum ADC input levels).

If the input signal is too large however and causes the

ADC to clip, the STLC1511 will report to the digital

chip that a clip has occurred. This is accomplished by

forcing the output data stream supplied to the digital

chip to either “7FFF” hex for an out of range positive

input or to “8000” hex for an out of range negative in-

put. This is highlighted in Figure 10.

T X S IN [1:0]

FR M C LK

RX S O UT[1:0]

CK 35M

SDATA

SOUT

8-bit Shift Register (x2)

to DAC parallel input

(N ote: D AC input is

CKD AC

(4.416M H z Clock from PLL)

SD ATA

SOU T

8-bit Shift Register (x2)

from AD C parallel output

(Note: AD C output changes

O U T[15:0]

D ATA [15:0]

CK35M

FRM CLK

TXSIN [0]

TXSIN [1]

msb

a12

a11

a10

lsb

(x14)

(x12)

msb

b10

RXSO U T[0]

RXSO U T[1]

lsb

D ata[15:0]

O ut[15:0]

CK AD C

(4.416MH z Clock from PL L)

(x2)

(4 D ff to align data

edges as required)

on posedge of C KADC )

sampled on posedge

CKDAC)

CKD AC

CK AD C

D ata clocked out by

A D C on this edge

Data sampled by

D A C on this edge

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