STLC1511

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59

QVEEDAC

VEE

VSSCO

Quiet ground for DAC circuitry

60

RESETN

DI

TLCHT

ResetN for the AFE

61

TXSIN[0]

DI

TLCHT

Tx serial data (lsb) input

62

TXSIN[1]

DI

TLCHT

Tx serial data (msb) input

63

FRMCLK

DO

BT4CR

Tx 4.416MHz frame clock reference output

64

VSSDIG1

VSS

VSSCO

Ground (digital) for ADC and DAC

<1>HCMOS5 guidelines are for 1 pair of power/ground for 4 output drivers (4mA)

<2>Pins 35 and 43 are both connected to the analog VCC supplying the on chip oscillator. Similarly, Pins 34 and 42 are connected

to analog VSS for the oscillator. Supply line inductance is reduced using two pads for VCC (and VSS) in this manner. At the board

level, Pins 35 and 43 should be connected to analog VCC, and pins 34 and 42 should be connected to analog VSS.

Table 1. Pin Assignement

Pin #

Pin Name

Pin Type

Pad Type

Description

3.0 FUNCTIONAL DESCRIPTION

3.1 General Functional Description

The STLC1511 consists of the following functional

blocks:

s

Transmit Signal Path

s

Receive Signal Path

s

Phase Lock Loop and Amplifier for an external

oscillator.

s

Bias Voltage and Current Generation

s

Digital Interface

s

Serial Interface

The transmit path contains the 14-bit digital to analog

converter (DAC) necessary to generate the transmit

signal from a 14-bit digital input word. This transmit

signal is then scaled by the on chip programmable

gain amplifier (TxPGA) from 0 to -32dB in 2dB steps.

The scaled output signal is then driven off chip to the

external filters and power amplifier (PA) which drives

the DMT signal to the subscriber loop. The transmit

path is fully differential but may be used single ended

if both outputs from the TxPGA are terminated cor-

rectly.

The receive path contains an optional unity gain buff-

er followed by a two stage programmable gain ampli-

fier (RxPGA), a 1st order low pass anti-aliasing filter,

and a 12-bit analog to digital converter (ADC). The

RxPGA consists of two stages and the gain is digitally

programmable from 0 to 40dB in 0.5dB steps. The re-

ceive path is fully differential but may be used single

ended provided the other input to the RxPGA is

grounded.

The STLC1511 contains the circuits required to con-

struct a PLL that generates either a 17.644MHz/

35.328 MHz clock from a 2.56 MHz reference clock

when supplied with an external LC or crystal oscilla-

tor and tuning circuit. This clock is supplied to the

both the transmit and receive converters, and the se-

rial interface used to transfer the Rx/Tx data between

the STLC1511 and digital chip. The STLC1511 also

has the ability to be driven directly by an external

35.328MHz clock supplied to the FREF pin.

The bias circuitry contains a bandgap voltage refer-

ence from which the converter references and analog

ground voltage is generated. This block also gener-

ates an accurate current using an external resistor

from which all of the STLC1511 circuits are biased. In

addition, the bias circuitry also generates a 2.5V ref-

erence for the external Vco/Vcxo components and

can be used for other external circuits if necessary.

There is a 4 pin serial digital interface (DTX, DRX,

DIGCLK, ENB) that loads a one of four 8-bit control

register that controls all the programmable features

on the STLC1511. Refer to “Digital Interface And

Memory Map” on page 20 for more information on

the programmability of the AFE.

To facilitate data transfer between the STLC1511

and the digital ASIC (STLC1510), a 2-bit wide serial

interface for the transmit path and a 2-bit wide serial

interface for the receive path is incorporated into the

AFE. This interface consists of two transmit pins (TX-

SIN[0:1]), two receive pins (RXSOUT[1:0]), and the

necessary control signals (FRMCLK, CK35M) to

transmit the required data. For more information See

“Serial Interface” on page 18.