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STLC1511

Table 5. CO PLL Specifications

Unless otherwise noted, typical specifications apply for VCC=5.0 V, temperature=25×C, nominal process and bias

Description

min

typ

max

Units

Comments

Reference Clock Frequency

2.56

MHz

on pin FREF

Output Clock Frequency

17.644

MHz

at pin DIGREF

LC Frequency Tuning

84

88.32

94

MHz

Assumes 2% capacitors.

Oscillator Signal Level

200

500

mVp

Power Up Time

200

msec

VCO Gain

Vco gain (LC)

5.0

5.4

6

MHz/V

see CAPTION FIGURE 4

on page 14

Charge Pump Current

180

200

220

mA

Input Impedance @OSCPB and

<1>Input and output impedance measured with 50kW from OSCPB to Vcc and OSCNB to Vcc

see TITLE 3 3.4.3 on page

16

Output Impedance @OSCPE

see TITLE 3 3.4.3 on page

16

2

5KHz offset

10kHz offset

20kHz offset

30kHz offset

100kHz offset

200kHz offset

300kHz offset

400kHz offset

500kHz offset

<2>For inband noise, phase noise at multiples of 4.3125kHz will rms add to degrade the inband SNR. Similarly, for out of band signals,

phase noise will rms add depending on the offset between the carrier and the band of interest to reduce the SNR. For example,

noise contributions on carriers from 34 to 127 will rms add to degrade the SNR on the edge of the US band (carrier 26).

89

91

97

101

120

129

133

137

141

dBc/Hz

Phase noise at DIGREF

output (i.e. 17.664MHz) in

CO Oscillator mode.