Sampling Period

1/2 Sampling Period (see Note)

FS

TxDI

HC1, HC0

1X

Data Word Input

Control Word

01

SCLK

TxDO

Data Word Output

Register Word

Note : In slave mode, this 1/2 Sampling Period is not mandatory. If 1/2 Sampling Period is not provided, one sample is lost.

Figure 8 : Mixed Mode

5 - HOST INTERFACE

FUNCTIONAL DESCRIPTION (continued)

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

-

D15 D14

-

-

-

-

FS

SCLK

TxDI

HC1, HC0

Sampling period

00 or 01

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

-

D15 D14

-

-

-

-

TxDO

Figure 7 : Data Mode

The Host interface consist of the shift clock,

the frame synchronization signal, the ADC-

channel data output, and the DAC-channel

data input.

Two modes of serial transfer are available :

- First : Software mode for 15-bit transmit data

transfer and 16-bit receive data transfer

- Second : hardware mode for 16-bit data transfer.

Both modes are selected by the Hardware Control

pins (HC0, HC1).

The data to the device, input/output are MSB-first

in 2’s complement format (see Table 2).

When Control Mode is selected, the device will

internally generate an additional Frame Synchroni-

zation Pulse (Secondary Frame Synchronization

Pulse) at the midpoint of the original Frame Period.

If the device is in slave mode the additional frame

sync (secondary frame sync pulse) must be gener-

ated by the processor. The Original Frame Syn-

chronization Pulse will also be referred to as the

Primary Frame Synchronization Pulse.

Table 2 : Mode Selection

HC1

HC0

LSB

Useful Data

Secondary

FSYNC

Description

0

0

0

15bits

No

Software Mode for Data Transfer only.

0

0

1

15bits (+16bits reg.)

Yes

Software Mode for Data Transfer + Control Register Transfer.

0

1

X

16bits

No

Hardware Mode for Data Transfer only.

1

X

X

16bits (+16bits reg.)

Yes

Hardware Mode for Data Transfer + Control Register Transfer.

STLC7550

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