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STLC7550 数据表(PDF) 12 Page - STMicroelectronics |
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STLC7550 数据表(HTML) 12 Page - STMicroelectronics |
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12 / 17 page ![]() Nominal AC Electrical Characteristics (Reference level VIL = 0.5V, VIH = DVDD - 0.5V, VOL = 0.3V, VOH = DVDD - 0.5V, DVDD = 3V, Output load = 50pF unless otherwise) Symbol N° Parameter Min. Typ. Max. Unit SERIAL CHANNEL TIMING (see Figure 9 for Parameter numbers) 1 SCLK Period 300 ns 2 SCLK Width Low 150 ns 3 SCLK Width High 150 ns 4 SCLK Rise Time 10 ns 5 SCLK Fall Time 10 ns 6 FS Setup 100 ns 7 FS Hold 100 ns 8 DIN Setup 50 ns 9 DIN Hold 0 ns 10 DOUT Valid 20 ns 11 HC0,HC1 Set-up 20 ns 12 0 50 ns MASTER CLOCK INTERFACE (MCLK) (MCM = 0) MCLK Master Clock Input 0.92 1.54 2.8 MHz Master Clock Duty Cycle 45 55 % ELECTRICAL SPECIFICATIONS (continued) SCLK FS DIN 1 67 10 89 2.4 35 MSB MSB DOUT HC0 11 12 Figure 9 : Serial Interface Timing Diagram STLC7550 12/17 |
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