DEFINITION AND TERMINOLOGY

Data Transfer Interval

interval is 16 shift clocks provides by the chip.

Signal Data

This refers to the input signal and all the converted representations

through the ADC channel and the DAC channel.

Data Mode

This refers to the data transfer. Since the device is synchronous, the

signal data words from the ADC channel and to the DAC channel occur

simultaneously.

Control Mode

This refers to the digital control data transfer into DIN and the register

requested by hardware or software.

Frame Sync.

Frame sync refers only to the falling edge of the signal which initiates

the data transfer interval. The primary frame sync starts the Data Mode

and the secondary frame sync starts the Control Mode.

Frame Sync and

Sampling Period

The time between falling edges of successive primary frame sync

signals.

ADC Channel

This term refers to all signal processing circuits between the analog

DAC Channel

This term refers to all signal processing circuits between the digital

available at OUT+ and OUT- pins.

OverSampling Ratio

This term refer to the ratio between the master clock MCLK

corresponding to the oversampling frequency and the sampling

frequency FS.

Resolution

The number of bits in the input words to the DAC, and the output words

in the ADC.

Dynamic Range

The S/(N+D) with a 1kHz, -20dBr input signal and extrapolated to full

scale. Use of a small input signal reduces the harmonic distortion

explained before.

Signal-to-(Noise+Distortion)

S/(THD+N) is the ratio of the rms of the input signal to the rms of all

other spectral components within the measurement bandwidth

(0.425 x Sampling Frequency). Units in dB.

Crosstalk

The amount of 1kHz signal present on the output of the grounded input

channel with 1kHz 0dB signal present on the other channel. Units

in dB.

Power Supply Rejection Ratio

PSRR. The amount of 1kHz signal present on the output of the

power supply.

STLC7550

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