6 - CONTROL REGISTER

This section defines the control and device status

information. The register programming occurs only

during Secondary Frame Synchronization. After a

reset condition, the device is always in data mode.

Table 3 : Bits Assignment

Bits

Name

Function

Reset

Value

0-

-

0

1

D1

Aux/Main Input

0

2

D2

Receive Gain

0

3

D3

Oversampling bit 0

0

4

D4

Oversampling bit 1

0

5

D5

Oversampling bit 2

0

6

D6

Attenuator transmit bit 0

0

7

D7

Attenuator transmit bit1

0

8

M

M Divider

1

9

Q0

Q0 Divider

1

10

Q1

Q1 Divider

0

11

Q2

Q2 Divider

0

12

T0

M Divider and Test mode bit 0

0

13

T1

M Divider and Test mode bit 1

0

14

TEST2

Test mode bit 2

0

15

TEST3

Test mode bit 3

0

Table 4 : Aux/Main Input

D1

Function

0

Main Receive Input

1

Auxiliary Receive Input

Table 5 : Receive Gain

D2

Function

DIFFERENTIAL INPUT

0

0dB gain (commun mode fixed)

1

+6dB gain (commun mode non-fixed)

0

-6dB gain (see Note 1)

1

0dB gain

Note 1 : Not recommended case. Performances could be reduced.

Table 6 : Oversampling Ratio

D5

D4

D3

Function

0

0

0

160

0

0

1

192

0

1

0

Reserved

0

1

1

Reserved

1

0

0

Reserved

10

1

64

11

0

96

1

1

1

128

Table 7 : Transmit Attenuation

D7

D6

Function

0

0

Infinite

0

1

Reserved

1

0

-6dB

11

0dB

Table 8 : Q Divider Clock Generator

D11

D10

D9

Function

0

0

0

Q divider = 5

0

0

1

Q divider = 6

0

1

0

Q divider = 7

0

1

1

Q divider = 8

1

0

0

Q divider = 4.5

1

0

1

Q divider = 5.5

1

1

0

Q divider = 6.5

1

1

1

Q divider = 7.5

Table 9 : M Divider Clock Generator

D13

D12

D8

Function

0

0

0

M divider = 3

0

0

1

M divider = 4

0

1

X

Reserved

1

0

X

Reserved

1

1

0

M divider = 1

1

1

1

M divider = 2

Table 10 : Reserved Mode

D15

D14

Function

X

X

Reserved for test

This two bits must be set to 0 for normal operation.

FUNCTIONAL DESCRIPTION (continued)

STLC7550

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