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PM6670AS 数据表(PDF) 11 Page - STMicroelectronics

部件名 PM6670AS
功能描述  Complete DDR2/3 memory power supplies controller
PDF  54 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

PM6670AS 数据表(HTML) 11 Page - STMicroelectronics

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PM6670AS
Electrical characteristics
11/54
Symbol
Parameter
Test condition
Min
Typ
Max
Unit
VDDQ Output threshold
synchronous for final tracking
to non-tracking discharge
transition
0.2
0.4
0.6
V
VTT LDO section
ILDOIN,ON
LDO input bias current in full-
on state
S3 = S5 = +5 V,
No Load on VTT
110
µA
ILDOIN,
STR
LDO input bias current in
suspend-to-RAM state
S3 = 0 V, S5 = +5 V,
No Load on VTT
10
ILDOIN,
STD
LDO input bias current in
suspend-to-disk state
S3 = S5 = 0 V, No Load on VTT
1
IVTTSNS,
BIAS
VTTSNS bias current
S3 = +5 V, S5 = +5 V,
VVTTSNS = VVSNS /2
1
µA
IVTTSNS,
LEAK
VTTSNS leakage current
S3 = 0V, S5 = +5 V,
VVTTSNS = VVSNS /2
1
IVTT,LEAK VTT leakage current
S3 = 0V, S5 = +5 V,
VVTT = VVSNS /2
-10
10
VVTT
LDO linear regulator output
voltage (DDR2)
S3 = S5= +5 V, IVTT = 0 A,
MODE = DDRSEL = +5 V
0.9
V
LDO linear regulator output
voltage (DDR3)
S3 = S5= +5 V, IVTT = 0 A,
MODE = +5 V, DDRSEL = 0 V
0.75
LDO output accuracy respect
to VTTREF
S3 = S5 = MODE = + 5 V,
-1 mA < IVTT < 1 mA
-20
20
mV
S3 = S5 = MODE = +5 V,
-1 A < IVTT < 1 A
-25
25
S3 = S5 = MODE = +5 V,
-2 A < IVTT < 2 A
-35
35
IVTT,CL
LDO source current limit
VVTT < 1.10*( VVSNS /2)
2
2.3
3
A
VVTT > 1.10*( VVSNS /2)
1
1.15
1.4
LDO sink current limit
VVTT > 0.90*( VVSNS /2)
-3
-2.3
-2
VVTT < 0.90*( VVSNS /2)
-1.4
-1.15
-1
VTTREF section
VVTTREF
VTTREF output voltage
IVTTREF = 0 A, VVSNS = 1.8 V
0.9
V
VTTREF output voltage
accuracy respect to VSNS/2
-15 mA < IVTTREF < 15 mA,
VVSNS = 1.8 V
-2
2
%
IVTTREF VTTREF current limit
VTTREF = 0 or VSNS
±40
mA
Table 6.
Electrical characteristics (continued)
TA = -25 °C to 85 °C , VCC = AVCC = +5 V and LDOIN connected to VDDQ output if not
otherwise specified (1)



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