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PM6670AS 数据表(PDF) 48 Page - STMicroelectronics |
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PM6670AS 数据表(HTML) 48 Page - STMicroelectronics |
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48 / 54 page  Application information PM6670AS 48/54 8.1.7 All ceramic capacitors application Design of external feedback network depends on the output voltage ripple across the output capacitors' ESR. If the ripple is great enough (at least 20 mV), the compensation network simply consists of a CINT capacitor. Figure 40. Integrative compensation The stability of the system depends firstly on the output capacitor zero frequency. It must be verified that: Equation 48 where k is a free design parameter greater than unity (k > 3) . It determines the minimum integrator capacitor value CINT: Equation 49 CFILT CINT RINT gm + - Vr=0.9 VSNS Ton One-shot generator VREF PWM Comparator + - COMP VDDQ Integrator out out Zout SW C R 2 k f k f ⋅ π = ⋅ > Vo Vref f k f 2 g C Zout SW m INT ⋅ ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ − ⋅ π > |
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