PM6670AS datasheet(49/54 Pages) STMICROELECTRONICS

49 / 54 page

PM6670AS

Application information

49/54

If the ripple on pin COMP is greater than the integrator output dynamic (150 mV), an

additional capacitor Cfilt could be added in order to reduce its amplitude. If q is the desired

attenuation factor of the output ripple, select:

Equation 50

In order to reduce noise on pin COMP, it's possible to introduce a resistor RINT that, together

with CINT and Cfilt, becomes a low psas filter. The cutoff frequency fCUT must be much

greater (10 or more times) than the switching frequency of the section:

Equation 51

For most of applications both RINT and Cfilt are unnecessary.

If the ripple is very small (e.g. such as with ceramic capacitors), an additional compensation

network, called "Virtual ESR" network, is needed. This additional part generates a triangular

ripple that substitutes the ESR output voltage ripple. The complete compensation scheme is

represented in Figure 41.

Figure 41. Virtual ESR network

)

(

INT

filt

−

⋅

FILT

INT

FILT

INT

CUT

INT

⋅

VREF

CFILT

CINT

RINT

PWM Comparator

0.9V

VDDQ

Ton

Generation

Block

Integrator

PM6670AS 数据表(PDF) 49 Page - STMicroelectronics

PM6670AS 数据表(HTML) 49 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

数据表下载