STPCCLIENT datasheet(13/48 Pages) STMICROELECTRONICS

13 / 48 page

PIN DESCRIPTION

Issue 1.7 - February 8, 2000

13/48

RTCRW#* / DD[13]

I/O

RTC Read/Write / Data Bus bit 13 (IDE)

RTCDS#* / DD[12]

I/O

RTC Data Strobe / Data Bus bit 12 (IDE)

SA[19:8]* / DD[11:0]

I/O

Latched Address (ISA) / Data Bus (IDE)

SA[7:0]

I/O

Latched Address (IDE)

SD[15:0]*

I/O

Data Bus (ISA)

ISA/IDE COMBINED CONTROL

IOCHRDY* / DIORDY

I/O

I/O Channel Ready (ISA) - Busy/Ready (IDE)

ISA CONTROL

ALE*

Address Latch Enable

BHE#*

I/O

System Bus High Enable

MEMR#*, MEMW#*

I/O

Memory Read and Memory Write

SMEMR#*, SMEMW#*

System Memory Read and Memory Write

IOR#*, IOW#*

I/O

I/O Read and Write

MASTER#*

Add On Card Owns Bus

MCS16#*, IOCS16#*

Memory/IO Chip Select16

REF#*

Refresh Cycle.

AEN*

Address Enable

IOCHCK#*

I/O Channel Check.

ISAOE#*

Bidirectional OE Control

GPIOCS#*

I/O

General Purpose Chip Select

IDE CONTROL

PIRQ*

Primary Interrupt Request

SIRQ*

Secondary Interrupt Request

PDRQ*

Primary DMA Request

SDRQ*

Secondary DMA Request

PDACK#*

Primary DMA Acknowledge

SDACK#*

Secondary DMA Acknowledge

PIOR#*

I/O

Primary I/O Read

PIOW#*

Primary I/O Write

SIOR#*

I/O

Secondary I/O Read

SIOW#*

Secondary I/O Write

IPC

IRQ_MUX[3:0]*

Multiplexed Interrupt Request

DREQ_MUX[1:0]*

Multiplexed DMA Request

DACK_ENC[2:0]*

DMA Acknowledge

TC*

ISA Terminal Count

MONITOR INTERFACE

RED, GREEN, BLUE

Red, Green, Blue

VSYNC*

Vertical Synchronization

HSYNC*

Horizontal Synchronization

VREF_DAC

DAC Voltage reference

RSET

Resistor Set

COMP

Compensation

SCL / DDC[1]*

I/O

I C Interface - Clock / Can be used for VGA DDC[1] signal

Table 2-2. Definition of Signal Pins

Signal Name

Dir

Description

Qty

Note; * denotes theat the pin is V5T (see Section 4. )

STPCCLIENT 数据表(PDF) 13 Page - STMicroelectronics

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