STPCCLIENT datasheet(16/48 Pages) STMICROELECTRONICS

16 / 48 page

PIN DESCRIPTION

16/48

Issue 1.7 - February 8, 2000

ODD_EVEN

Frame Synchronization.

VCS

Horizontal Line Synchronization.

2.2.5.

PCI INTERFACE

PCI_CLKI

33MHz PCI Input Clock This signal is

the PCI bus clock input and should be driven from

the PCI_CLKO pin.

PCI_CLKO

33MHz PCI Output Clock. This is the

master PCI bus clock output.

AD[31:0]

PCI Address/Data. This is the 32-bit PCI

multiplexed address and data bus. This bus is

driven by the master during the address phase

and data phase of write transactions. It is driven

by the target during data phase of read transac-

tions.

CBE#[3:0]

Bus Commands/Byte Enables. These

are the multiplexed command and Byte enable

signals of the PCI bus. During the address phase

they define the command and during the data

phase they carry the Byte enable information.

These pins are inputs when a PCI master other

than the STPC Client owns the bus and outputs

when the STPC Client owns the bus.

FRAME#

Cycle Frame. This is the frame signal of

the PCI bus. It is an input when a PCI master owns

the bus and is an output when STPC Client owns

the PCI bus.

TRDY#

Target Ready. This is the target ready sig-

nal of the PCI bus. It is driven as an output when

the STPC Client is the target of the current bus

transaction. It is used as an input when STPC Cli-

ent initiates a cycle on the PCI bus.

IRDY#

Initiator Ready. This is the initiator ready

signal of the PCI bus. It is used as an output when

the STPC Client initiates a bus cycle on the PCI

bus. It is used as an input during the PCI cycles

targeted to the STPC Client to determine when the

current PCI master is ready to complete the cur-

rent transaction.

STOP#

Stop Transaction. Stop is used to imple-

ment the disconnect, retry and abort protocol of

the PCI bus. It is used as an input for the bus cy-

cles initiated by the STPC Client and is used as an

output when a PCI master cycle is targeted to the

STPC Client.

DEVSEL#

I/O Device Select. This signal is used

as an input when the STPC Client initiates a bus

cycle on the PCI bus to determine if a PCI slave

device has decoded itself to be the target of the

current transaction. It is asserted as an output ei-

ther when the STPC Client is the target of the cur-

rent PCI transaction or when no other device as-

serts DEVSEL# prior to the subtractive decode

phase of the current PCI transaction.

PAR

Parity Signal Transactions. This is the parity

signal of the PCI bus. This signal is used to guar-

antee even parity across AD[31:0], CBE#[3:0],

and PAR. This signal is driven by the master dur-

ing the address phase and data phase of write

transactions. It is driven by the target during data

phase of read transactions. (Its assertion is identi-

cal to that of the AD bus delayed by one PCI clock

cycle)

SERR#

System Error. This is the system error sig-

nal of the PCI bus. It may, if enabled, be asserted

for one PCI clock cycle if the target aborts an

STPC Client initiated PCI transaction. Its assertion

by either the STPC Client or by another PCI bus

agent will trigger the assertion of NMI to the host

CPU. This is an open drain output.

LOCK#

PCI Lock. This is the lock signal of the PCI

bus and is used to implement the exclusive bus

operations when acting as a PCI target agent.

PCI_REQ#[2:0]

PCI Request. These pins are the

three external PCI master request pins. They indi-

cate to the PCI arbiter that the external agents re-

quire use of the bus.

PCI_GNT#[2:0]

PCI Grant. These pins indicate

that the PCI bus has been granted master, re-

questing it on its PCI_REQ#.

2.2.6.

ISA/IDE COMBINED ADDRESS/DATA

LA[23]/SCS3#

Unlatched Address (ISA) / Sec-

ondary Chip Select (IDE). This pin has two func-

tions, depending on whether the ISA bus is active

or the IDE bus is active.

When the ISA bus is active, this pins is ISA Bus

unlatched address bit 23 for 16-bit devices. When

ISA bus is accessed by any cycle initiated from

PCI bus, this pin is in output mode. When an ISA

bus master owns the bus, this pins is in input

mode.

When the IDE bus is active, this signals is used as

the active high secondary slave IDE chip select

signal. This signal is to be externally NANDed with

the ISAOE# signal before driving the IDE devices

to guarantee it is active only when ISA bus is idle.

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