STPCCLIENT datasheet(3/48 Pages) STMICROELECTRONICS

3 / 48 page

STPC CLIENT

Issue 1.7 - February 8, 2000

3/48

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ISA master/slave

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The ISA clock generated from either

14.318MHz oscillator clock or PCI clock

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Supports programmable extra wait state for

ISA cycles

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Supports I/O recovery time for back to back I/

O cycles.

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Fast Gate A20 and Fast reset.

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Supports the single ROM that C, D, or E.

blocks shares with F block BIOS ROM.

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Supports flash ROM.

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Buffered DMA & ISA master cycles to reduce

bandwidth utilization of the PCI and Host bus.

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IDE Interface

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Supports PIO

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Supports up to Mode 5 Timings

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Supports up to 4 IDE devices

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Individual drive timing for all four IDE devices

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Concurrent channel operation (PIO modes) -

4 x 32-Bit Buffer FIFO per channel

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Support for PIO mode 3 & 4

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Support for 11.1/16.6 MB/s, I/O Channel

Ready PIO data transfers.

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Supports both legacy & native IDE modes

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Supports hard drives larger than 528MB

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Support for CD-ROM and tape peripherals

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Backward compatibility with IDE (ATA-1).

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Integrated peripheral controller

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2X8237/AT compatible 7-channel DMA con-

troller.

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2X8259/AT compatible interrupt Controller.

16 interrupt inputs - ISA and PCI.

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Three 8254 compatible Timer/Counters.

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Power Management

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Four power saving modes: On, Doze, Stand-

by, Suspend.

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Programmable system activity detector

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Supports SMM.

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Supports STOPCLK.

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Supports IO trap & restart.

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Independent peripheral time-out timer to

monitor hard disk, serial & parallel ports.

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Supports RTC, interrupts and DMAs wake-up

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