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STPCCLIENT 数据表(PDF) 33 Page - STMicroelectronics |
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STPCCLIENT 数据表(HTML) 33 Page - STMicroelectronics |
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33 / 48 page  ELECTRICAL SPECIFICATIONS Issue 1.7 - February 8, 2000 33/48 Table 4-4. PCI Bus AC Timing Name Parameter Min Max Unit t1 PCI_CLKI to AD[31:0] valid 2 13 ns t2 PCI_CLKI to FRAME# valid 2 11 ns t3 PCI_CLKI to CBE#[3:0] valid 2 12 ns t4 PCI_CLKI to PAR valid 2 12 ns t5 PCI_CLKI to TRDY# valid 2 13 ns T6 PCI_CLKI to IRDY# valid 2 11 ns T7 PCI_CLKI to STOP# valid 2 14 ns T8 PCI_CLKI to DEVSEL# valid 2 11 ns T9 PCI_CLKI to PCI_GNT# valid 2 14 ns t10 AD[31:0] bus setup to PCI_CLKI 7 ns t11 AD[31:0] bus hold from PCI_CLKI 3 ns t12 PCI_REQ#[2:0] setup to PCI_CLKI 10 ns t13 PCI_REQ#[2:0] hold from PCI_CLKI 1 ns t14 CBE#[3:0] setup to PCI_CLKI 7 ns t15 CBE#[3:0] hold to PCI_CLKI 5 ns t16 IRDY# setup to PCI_CLKI 7 ns t17 IRDY# hold to PCI_CLKI 4 ns t18 FRAME# setup to PCI_CLKI 7 ns t19 FRAME# hold from PCI_CLKI 3 ns Table 4-5. DRAM Bus AC Timing Name Parameter Min Max Unit t22 HCLK to RAS#[3:0] valid 17 ns t23 HCLK to CAS#[7:0] bus valid 17 ns t24 HCLK to MA[11:0] bus valid 17 ns t25 HCLK to MWE# valid 17 ns t26 HCLK to MD[63:0] bus valid 25 ns t27 MD[63:0] Generic setup 7 ns t28 GCLK2X to RAS#[3:0] valid 17 ns t29 GCLK2X to CAS#[7:0] valid 17 ns t30 GCLK2X to MA[11:0] bus valid 17 ns t31 GCLK2X to MWE# valid 17 ns t32 GCLK2X to MD[63:0] bus valid 23 ns t33 MD[63:0] Generic hold 0 ns |
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