M24M01-R, M24M01-W, M24M01-HR

Device operation

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3.6

Write operations

Following a Start condition the bus master sends a device select code with the R/W bit (RW)

reset to 0. The device acknowledges this, as shown in Figure 8, and waits for two address

bytes. The device responds to each address byte with an acknowledge bit, and then waits

for the data byte.

Writing to the memory may be inhibited if Write Control (WC) is driven high. Any Write

instruction with Write Control (WC) driven high (during a period of time from the Start

condition until the end of the two address bytes) will not modify the memory contents, and

the accompanying data bytes are not acknowledged, as shown in Figure 7.

Each data byte in the memory has a 17-bit address (the most significant bit b16 is in the

device select code and the Least Significant Bits b15-b0 are defined in two address bytes).

The most significant byte (Table 3) is sent first, followed by the least significant byte

(Table 4).

bit” time slot), either at the end of a Byte Write or a Page Write, the internal memory Write

cycle is triggered. A Stop condition at any other time slot does not trigger the internal Write

cycle.

the device’s internal address counter is incremented automatically, to point to the next byte

address after the last one that was modified.

During the internal Write cycle, Serial Data (SDA) is disabled internally, and the device does

not respond to any requests.

3.7

Byte Write

After the device select code and the address bytes, the bus master sends one data byte. If

the addressed location is Write-protected, by Write Control (WC) being driven high, the

device replies with NoAck, and the location is not modified. If, instead, the addressed

location is not Write-protected, the device replies with Ack. The bus master terminates the

transfer by generating a Stop condition, as shown in Figure 8.

3.8

Page Write

The Page Write mode allows up to 256 bytes to be written in a single Write cycle, provided

that they are all located in the same ’row’ in the memory: that is, the most significant

memory address bits, b16-b8, are the same. If more bytes are sent than will fit up to the end

of the row, a condition known as ‘roll-over’ occurs. This should be avoided, as data starts to

become overwritten in an implementation dependent way.

The bus master sends from 1 to 256 bytes of data, each of which is acknowledged by the

device if Write Control (WC) is low. If Write Control (WC) is high, the contents of the

addressed memory location are not modified, and each data byte is followed by a NoAck.

After each byte is transferred, the internal byte address counter (the 8 least significant

address bits only) is incremented. The transfer is terminated by the bus master generating a

Stop condition.