HD6417618 datasheet(385/646 Pages) RENESAS

部件名	HD6417618

功能描述	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

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制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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Section 14 Serial Communication Interface with FIFO (SCIF)

Rev. 6.00 Jun. 12, 2007 Page 353 of 610

REJ09B0131-0600

14.3.9

FIFO Control Register (SCFCR)

SCFCR is a 16-bit register that resets the number of data in the transmit and receive FIFO

registers, sets the trigger data number, and contains an enable bit for loop-back testing. SCFCR

can always be read and written to by the CPU. It is initialized to H'0000 by a power-on reset.

Bit

Bit Name

Initial

value

R/W

Description

15 to 11



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

RSTRG2

RSTRG1

RSTRG0

R/W

RTS Output Active Trigger

When the number of receive data in the receive FIFO

shown below, the

RTS signal is set to high.

These bits are available only in SCFCR_0 and

SCFCR_1. In SCFCR_2, these bits are reserved. The

initial value is 0 and the write value should always be 0.

000: 15

001: 1

010: 4

011: 6

100: 8

101: 10

110: 12

111: 14

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