HD6417618 datasheet(106/646 Pages) RENESAS

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Section 5 Exception Handling

Rev. 6.00 Jun. 12, 2007 Page 74 of 610

REJ09B0131-0600

5.5

Exceptions Triggered by Instructions

5.5.1

Types of Exceptions Triggered by Instructions

Exception handling can be triggered by the trap instruction, illegal slot instructions, and general

illegal instructions, as shown in table 5.9.

Table 5.9

Types of Exceptions Triggered by Instructions

Type

Source Instruction

Comment

Trap instruction

TRAPA



Illegal slot

instructions*

Undefined code placed

immediately after a delayed

branch instruction (delay slot) or

instructions that changes the PC

value

Delayed branch instructions: JMP, JSR,

BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,

BRAF

Instructions that changes the PC value:

JMP, JSR, BRA, BSR, RTS, RTE, BT, BF,

TRAPA, BF/S, BT/S, BSRF, BRAF, LDC

Rm,SR, LDC.L @Rm+,SR

General illegal

instructions*

Undefined code anywhere

besides in a delay slot



Note:

The operation is not guaranteed when undefined instructions other than H'FC00 to

H'FFFF are decoded.

5.5.2

Trap Instructions

When a TRAPA instruction is executed, the trap instruction exception handling starts. The CPU

operates as follows:

1. The status register (SR) is saved to the stack.

2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the

instruction to be executed after the TRAPA instruction.

3. The CPU reads the start address of the exception handling routine from the exception handling

vector table that corresponds to the vector number specified in the TRAPA instruction,

program execution branches to that address, and then the program starts. This branch is not a

delayed branch.

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