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HD6417618 数据表(PDF) 109 Page - Renesas Technology Corp |
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HD6417618 数据表(HTML) 109 Page - Renesas Technology Corp |
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109 / 646 page  Section 5 Exception Handling Rev. 6.00 Jun. 12, 2007 Page 77 of 610 REJ09B0131-0600 5.7 Stack States after Exception Handling Ends The stack states after exception handling ends are shown in table 5.11. Table 5.11 Stack Status after Exception Handling Ends Types Stack State Address error (when the instruction that caused an exception is placed in the delay slot) SP Address of delayed branch instruction SR → 32 bits 32 bits Address error (other than above) SP SR → 32 bits 32 bits Address of instruction that caused exception Interrupt SP SR → 32 bits 32 bits Address of instruction after executed instruction Trap instruction SP SR → 32 bits 32 bits Address of instruction after TRAPA instruction |
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