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HD6417618 数据表(PDF) 133 Page - Renesas Technology Corp |
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HD6417618 数据表(HTML) 133 Page - Renesas Technology Corp |
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133 / 646 page ![]() Section 6 Interrupt Controller (INTC) Rev. 6.00 Jun. 12, 2007 Page 101 of 610 REJ09B0131-0600 Program execution state Interrupt? User break? I3 to I0 ≤ level 14? Level 14 interrupt? Level 1 interrupt? I3 to I0 ≤ level 13? I3 to I0 = level 0? No Yes No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Save SR to stack Save PC to stack Copy interrupt level to I3 to I0 Read exception vector table Branch to exception handling routine H-UDI interrupt? No Yes Level 15 interrupt? Note: I3 to I0 are Interrupt mask bits in the status register (SR) of the CPU NMI? I3 to I0 ≤ level 14? No Yes Figure 6.3 Interrupt Sequence Flowchart |
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