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HD6417618 数据表(PDF) 134 Page - Renesas Technology Corp |
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HD6417618 数据表(HTML) 134 Page - Renesas Technology Corp |
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134 / 646 page  Section 6 Interrupt Controller (INTC) Rev. 6.00 Jun. 12, 2007 Page 102 of 610 REJ09B0131-0600 6.6.2 Stack after Interrupt Exception Handling Figure 6.4 shows the stack after interrupt exception handling. 32 bits 32 bits PC*1 SR Address 4n – 8 4n – 4 4n SP*2 Notes: 1. PC is the start address of the next instruction (instruction at the return address) after the executed instruction. 2. Always make sure that SP is a multiple of 4 Figure 6.4 Stack after Interrupt Exception Handling 6.7 Interrupt Response Time Table 6.3 lists the interrupt response time, which is the time from the occurrence of an interrupt request until the interrupt exception handling starts and fetching of the first instruction of the interrupt handling routine begins. Figure 6.5 shows an example of the pipeline operation when an IRQ interrupt is accepted. |
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