HD6417618 datasheet(246/646 Pages) RENESAS

部件名	HD6417618

功能描述	32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7618 Series

PDF	646 Pages

Scroll/Zoom	100%

制造商	RENESAS [Renesas Technology Corp]

网页	http://www.renesas.com

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246 / 646 page

Section 9 Watchdog Timer (WDT)

Rev. 6.00 Jun. 12, 2007 Page 214 of 610

REJ09B0131-0600

9.3.4

Using Interval Timer Mode

When operating in interval timer mode, interval timer interrupts are generated at every overflow of

the counter. This enables interrupts to be generated at set periods.

1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and

set the initial value of the counter in WTCNT.

2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode.

3. When the WTCNT overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval

timer interrupt request is sent to the INTC. The WTCNT then resumes counting.

9.4

Usage Note

Note the following when using the WDT.

1. When using the WDT in interval mode, no overflow occurs by the H'00 immediately after

writing H'FF to WDTCNT. (IOVF in WTCSR is not set.) The overflow occurs at a point when

the count reaches H'00 after one cycle.

This does not occur when the WDT is used in watchdog timer mode.

HD6417618 数据表(PDF) 246 Page - Renesas Technology Corp