HD6417618 datasheet(294/646 Pages) RENESAS

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Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 6.00 Jun. 12, 2007 Page 262 of 610

REJ09B0131-0600

Bit

Bit Name

Initial

value

R/W

Description

SWR

R/W

Software Reset

Writing 1 in this bit initializes registers of the E-DMAC

other than TDLAR, RDLAR, and RMFCR and registers

of the EtherC. While a software reset is issued (64

cycles of the internal bus clock B

φ), accesses to the all

Ethernet-related registers are prohibited.

Software reset period (example):

When B

φ = 50 MHz: 1.28 µS

When B

φ = 33 MHz: 1.94 µS

This bit is always read as 0.

0: Writing 0 is ignored (E-DMAC operation is not

affected)

1: Writing 1 resets the EtherC and E-DMAC and then

automatically cleared

12.2.2

E-DMAC Transmit Request Register (EDTRR)

The EDTRR is a 32-bit readable/writable register that issues transmit directives to the E-DMAC.

When transmission of one frame is completed, the next descriptor is read. If the transmit

descriptor active bit in this descriptor has the "active" setting, transmission is continued. If the

transmit descriptor active bit has the "inactive" setting, the TR bit is cleared and operation of the

transmit DMAC is halted.

Bit

Bit Name

Initial

value

R/W

Description

31 to 1



All 0

Reserved

These bits are always read as 0. The write value should

always be 0.

R/W

Transmit Request

0: Transmission-halted state. Writing 0 does not stop

transmission. Termination of transmission is

controlled by the active bit in the transmit descriptor

1: Start of transmission. The relevant descriptor is read

and a frame is sent with the transmit active bit set to

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