HD6417618 datasheet(297/646 Pages) RENESAS

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Section 12 Ethernet Controller Direct Memory Access Controller (E-DMAC)

Rev. 6.00 Jun. 12, 2007 Page 265 of 610

REJ09B0131-0600

12.2.6

EtherC/E-DMAC Status Register (EESR)

EESR is a 32-bit readable/writable register that shows communications status information on the

E-DMAC in combination with the EtherC. The information in this register is reported in the form

of interrupts. Individual bits are cleared by writing 1 (however, bit 22 (ECI) is a read-only bit and

not to be cleared by writing 1) and are not affected by writing 0. Each interrupt source can also be

masked by means of the corresponding bit in the EtherC/E-DMAC status interrupt permission

The interrupts generated by this register are EINT0. For interrupt priority, see section 6.5,

Interrupt Exception Handling Vector Table.

Bit

Bit Name

Initial

value

R/W

Description



Reserved

This bit is always read as 0. The write value should

always be 0.

TWB

R/W

Write-Back Complete

Indicates that write-back from the E-DMAC to the

corresponding descriptor has completed. This

operation is enabled when the TIS bit in TRIMD is set

to 1.

0: Write-back has not completed, or no transmission

directive

1: Write-back has completed

29 to 27



All 0

Reserved

These bits are always read as 0. The write value

should always be 0.

TABT

R/W

Transmit Abort Detection

Indicates that the EtherC aborts transmitting a frame

because of failures during transmitting the frame.

0: Frame transmission has not been aborted or no

transmit directive

1: Frame transmit has been aborted

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