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CMS3216LAH 数据表(PDF) 11 Page - FIDELIX

部件名 CMS3216LAH
功能描述  32M(2Mx16) Low Power SDRAM
PDF  46 Pages
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制造商  FIDELIX [FIDELIX]
网页  http://www.fidelix.co.kr
标志 FIDELIX - FIDELIX

CMS3216LAH 数据表(HTML) 11 Page - FIDELIX

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Rev0.2, Jan. 2007
CMS3216LAx-75xx
EXTENDED MODE REGISTER
The Extended Mode Register controls additional functions such
as Partial Array Self Refresh (PASR), and Output Drive
Strength.The Extended Mode Register is programmed via the
Mode Register Set command (BS=1) and retains the stored
information until it is programmed again or the device loses
power. The Extended Mode Register must be programmed with
M8 through M10 set to “0”. The Extended Mode Register must
be loaded when all banks are idle and no bursts are in progress,
and the controller must wait the specified time initiating any
subsequent operation. Violating either of these requirements
results in unspecified operation.
AUTO TEMPERATURE COMPENSATED SELF REFRESH
Every cell in the DRAM requires refreshing due to the capacitor
losing its charge over time. The refresh rate is dependent on
temperature. At higher temperatures a capacitor loses charge
quicker than at lower temperatures, requiring the cells to be
refreshed more often. In order to save power consumption,
according to the temperature, Mobile-SDRAM includes the
internal temperature sensor and control units to control the self
refresh cycle automatically.
PARTIAL ARRAY SELF REFRESH
The Partial Array Self Refresh (PASR) feature allows the
controller to select the amount of memory that will be refreshed
during SELF REFRESH. The refresh options are all banks
(banks 0, 1); one bank (bank 0 or 1 by M7). WRITE and READ
commands occur to any bank selected during standard
operation, but only the selected banks in PASR will be
refreshed during SELF REFRESH. The data in banks 1 will be
lost when the one bank option with M7=0 is used. Similarly the
data will be lost in bank 0 when the one bank option with M7=1
is used down
.
Driver Strength Control
The driver strength feature allows one to reduce the drive
strength of the I/O’s on the device during low frequency
operation. This allows systems to reduce the noise associated
with the I/O’s switching.
Table 4. Extended Mode Register Definition
0
0
Bank
Up/Down
All must be set to ‘0’
Driver Strength
EM6-
A6
EM5-
A5
EM4-
A4
EM3-
A3
PASR
EM2-
A2
EM1-
A1
EM9-
A9
EM8-
A8
EM7-
A7
EM0-
A0
EM10-
A10
EM11-
BS
1



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