CMS3216LAH datasheet(19/46 Pages) FIDELIX

19 / 46 page

Rev0.2, Jan. 2007

CMS3216LAx-75xx

Operation

BANK / ROW ACTIVATION

Before any READ or WRITE commands can be issued to a

bank within the SDRAM, a row in that bank must be “opened”

(activated). This is accomplished via the ACTIVE command,

which selects both the bank and the row to be activated. A

READ or WRITE command may then be issued to that row,

subject to the tRCD specification. tRCD (MIN) should be divided

by the clock period and rounded up to the next whole number to

determine the earliest clock edge after the ACTIVE command

on which a READ or WRITE command can be entered. For

example, a tRCD specification of 20ns with a 125 Mhz clock

(8ns period) results in 2.5 clocks, rounded to 3. (The same

procedure is used to convert other specification limits from time

units to clock cycles.) A subsequent ACTIVE command to a

different row in the same bank can only be issued after the

previous active row has been “closed” (precharged). The

minimum time interval between successive ACTIVE commands

to the same bank is defined by tRC. A subsequent ACTIVE

command to another bank can be issued while the first bank is

being accessed, which results in a reduction of total row-access

overhead. The minimum time interval between successive

ACTIVE commands to different banks is defined by t tRRD.

READs

READ bursts are initiated with a READ command, as shown in

Figure 3. The starting column and bank addresses are provided

with the READ command, and auto precharge is either enabled

or disabled for that burst access. For the generic READ comm-

ands used in the following illustrations, auto precharge is disab-

led. During READ bursts, the valid data-out element from the

starting column address will be available following the CAS

latency after the READ command. Each subsequent data-out

element will be valid by the next positive clock edge. Figure 2.

shows general timing for each possible CAS latency setting.

Upon completion of a burst, assuming no other commands

have been initiated, the DQs will go High-Z. A fullpage burst will

continue until terminated. (The burst will wrap around at the end

of the page). A continuous flow of data can be maintained by

having addtional Read Burst or single Read Command. The

first data element from the new burst follows either the last

element of a completed burst or the last desired data element of

a longer burst that is being truncated.

The new READ command should be issued x cycles before the

clock edge at which the last desired data element is valid,

where x equals the CAS latency minus one.

This is shown in Figure 4. for CAS latencies of one, two and

three; data element n + 3 is either the last of a burst of four or

the last desired of a longer burst. Full-speed random read

accesses can be performed to the same bank, as shown in

Figure 5. , or each subsequent READ may be performed to a

different bank.

Figure 3. Read Command

CLK

CKE

/CS

/RAS

/CAS

/WE

A0-A8

A10

Read Command

High

Column

Address

Bank

Address

Enable Auto Precharge

Disable Auto Precharge

Don’t Care

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