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CMS3216LAH 数据表(PDF) 28 Page - FIDELIX

部件名 CMS3216LAH
功能描述  32M(2Mx16) Low Power SDRAM
PDF  46 Pages
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制造商  FIDELIX [FIDELIX]
网页  http://www.fidelix.co.kr
标志 FIDELIX - FIDELIX

CMS3216LAH 数据表(HTML) 28 Page - FIDELIX

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Rev0.2, Jan. 2007
CMS3216LAx-75xx
Figure 11. Read & Write Cycle at Same Bank @Burst Length=4, tDPL =2CLK (100Mhz)
Note :
45. Minimum row cycle times is required to complete internal DRAM operation.
46. Row precharge can interrupt burst on any cycle.[CAS Latency -1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(t SHZ) after
the clock.
47. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC
48. Out put will be Hi-Z after the end of burst. (1,2,3,8 & Full page bit burst)
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
Don’t Care
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
CLOCK
CKE
tRC
*note 45.
tRCD
/CS
/RAS
/CAS
RAa
CAa
RAb
CAb
ADDR
BS
RAb
RAa
A10/AP
CL=2
tOH
tSAC
tRAC
tSHZ *note 48.
*note 47.
tDPL
Qa0
Qa1
Qa2
Qa3
Qb0
Qb1
Qb2
Qb3
tOH
tSAC
tRAC
tSHZ *note 48.
*note 47.
tDPL
CL=3
/WE
DQM
Row Active
(A-Bank)
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
Precharge
(A-Bank)
*note 46.
DQ
tRP



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