CMS3216LAH datasheet(16/46 Pages) FIDELIX

16 / 46 page

Rev0.2, Jan. 2007

CMS3216LAx-75xx

Table 8. IDD Specifications and Conditions [21.22.26.27.].

Note :

21. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-40°C = TA = +85°C for IT parts) is ensured.

22. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VDD and VDDQ must be

powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh

requirement is exceeded.

23. All states and sequences not shown are illegal or reserved.

24. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.

25. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet tOH before going High-Z.

26. AC timing and IDD tests have VIL and VIH, with timing referenced to VIH/2 = crossover point. If the input transition time is longer than tT (MAX), then the timing is referenced

at VIL (MAX) and VIH (MIN) and no longer at the VIH/2 crossover point.

27. IDD specifications are tested after the device is properly initialized.

28. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open.

29. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition.

30. Address transitions average one transition every two clocks.

31. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels.

32. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD 6 limit is actually a nominal value and does not result in a fail value

TA=25℃, f=1Mhz, VDD(typ)

Test Conditions

Units

CIN

Max

Output Capacitance

COUT

Input Capacitance

Description

Parameter

Capacitance

AC Test Loads

OUTPUT

Z0=50

㎃

Operating Current : Burst Mode ; Continuous Burst ; Read or Write ; All banks

Active ; CAS Latency =3[28.29.30.]

IDD4

㎃

Active Standby Current in non Power Down Mode ; CS#=HIGH ; CKE=HIGH ; All

banks active after tRCD met ; No access in progress[28.30.31.]

IDD3n

㎃

Auto Refresh Current : tRC=tRC(min) CAS Latency=3 ; CKE,CS#=HIGH[28.29.30.32.32.]

IDD5

㎂

200

Self Refresh Current : CKE <=0.2V, 2 Banks

IDD6

㎂

150

Self Refresh Current : CKE <=0.2V, 1 Banks

㎂

Deep power down

IDD7

㎃

Precharge Standby Current in non ower down Mode; CKE=HIGH ; All banks Idle

IDD2n

㎃

Active Standby Current in Power Down Mode ; CS#=HIGH ; CKE=LOW ; All

banks active after tRCD met ; No access in progress[28.30.31.]

IDD3p

㎂

㎃

Units

IDD1

-75

300

Precharge Standby Current in Power Down Mode ; CKE=LOW ; All banks Idle

IDD2p

Operating Current : Active Mode ; Burst =1 ; Read or Write ; tRC= tRC(min);

CAS Latency =3 [28.29.30.]

Description

Parameter

30pF

VDDQ/2

CMS3216LAH 数据表(PDF) 16 Page - FIDELIX

CMS3216LAH 数据表(HTML) 16 Page - FIDELIX

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

数据表下载