PCM1795DB datasheet(33/58 Pages) TI

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PCM1795

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DFTH: Digital Filter Bypass (or Through Mode) Control

This bit is available for read and write.

Default value: 0

DFTH

Digital Filter Control

DFTH = 0

Digital filter enabled (default)

DFTH = 1

Digital filter bypassed for external digital filter

The DFTH bit is used to enable or disable the external digital filter interface mode.

MONO: Monaural Mode Selection

This bit is available for read and write.

Default value: 0

MONO

Mode Selection

MONO = 0

Stereo mode (default)

MONO = 1

Monaural mode

The MONO function is used to change operation mode from the normal stereo mode to the monaural mode.

When the monaural mode is selected, both DACs operate in a balanced mode for one channel of audio input

data. Channel selection is available for left-channel or right-channel data, determined by the CHSL bit.

CHSL: Channel Selection for Monaural Mode

This bit is available for read and write.

Default value: 0

CHSL

Channel Selection

CHSL = 0

Left channel selected (default)

CHSL = 1

Right channel selected

This bit is available when MONO = 1.

The CHSL bit selects left-channel or right-channel data to be used in monaural mode.

OS[1:0]:

ΔΣ Oversampling Rate Selection

These bits are available for read and write.

Default value: 00

OS[1:0]

Operating Speed Selection

64 times fS (default)

32 times fS

128 times fS

Reserved

The OS bits are used to change the oversampling rate of

ΔΣ modulation. Use of this function enables the

designer to stabilize the conditions at the post low-pass filter for different sampling rates. As an application

example, programming to set 128 times in 44.1-kHz operation, 64 times in 96-kHz operation, or 32 times in

192-kHz operation allows the use of only a single type (cut-off frequency) of post low-pass filter. The 128-fS

oversampling rate is not available at sampling rates above 100 kHz. If the 128-fS oversampling rate is selected, a

system clock of more than 256 fS is required.

In DSD mode, these bits are used to select the speed of the bit clock for DSD data coming into the analog FIR

filter.

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