 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
PCM1795DB 数据表(PDF) 28 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
PCM1795DB 数据表(HTML) 28 Page - Texas Instruments |
|
|
28 / 58 page  Register Map Register Definitions Register 16 R/W 0 0 1 0 0 0 0 ATL7 ATL6 ATL5 ATL4 ATL3 ATL2 ATL1 ATL0 Register 17 R/W 0 0 1 0 0 0 1 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 PCM1795 SLES248 – MAY 2009 ........................................................................................................................................................................................................ www.ti.com Table 8. User-Programmable Function Controls (continued) DF FUNCTION DEFAULT REGISTER BIT PCM DSD BYPASS FUNCTION AVAILABLE ONLY FOR READ Zero detection flag Not zero = 0 ZFGL (for left channel) Register 22 Yes Yes Yes Not zero, zero detected Zero detected = 1 ZFGR (for right channel) Device ID (at TDMCA) — Register 23 ID[4:0] Yes No No The mode control register map is shown in Table 9. Registers 16 to 21 include an R/W bit that determines whether a register read (R/W = 1) or write (R/W = 0) operation is performed. Registers 22 and 23 are read-only. Table 9. Mode Control Register Map REGISTER B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Register 16 R/W 0 0 1 0 0 0 0 ATL7 ATL6 ATL5 ATL4 ATL3 ATL2 ATL1 ATL0 Register 17 R/W 0 0 1 0 0 0 1 ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0 Register 18 R/W 0 0 1 0 0 1 0 ATLD FMT2 FMT1 FMT0 DMF1 DMF0 DME MUTE Register 19 R/W 0 0 1 0 0 1 1 REV ATS1 ATS0 OPE RSV DFMS FLT INZD Register 20 R/W 0 0 1 0 1 0 0 RSV SRST DSD DFTH MONO CHSL OS1 OS0 Register 21 R/W 0 0 1 0 1 0 1 RSV RSV RSV RSV RSV DZ1 DZ0 PCMZ Register 22 R 0 0 1 0 1 1 0 RSV RSV RSV RSV RSV RSV ZFGR ZFGL Register 23 R 0 0 1 0 1 1 1 RSV RSV RSV ID4 ID3 ID2 ID1 ID0 R/W: Read/Write Mode Select When R/W = 0, a write operation is performed. When R/W = 1, a read operation is performed. Default value: 0 ATx[7:0]: Digital Attenuation Level Setting These bits are available for read and write. Default value: 1111 1111b Each DAC output has a digital attenuator associated with it. The attenuator can be set from 0 dB to –120 dB, in 0.5-dB steps. Alternatively, the attenuator can be set to infinite attenuation (or mute). The attenuation data for each channel can be set individually. However, the data load control (the ATLD bit of control register 18) is common to both attenuators. ATLD must be set to '1' in order to change an attenuator setting. The attenuation level can be set using Equation 1: Attenuation level (dB) = 0.5 dB × (ATx[7:0]DEC – 255) Where, ATx[7:0]DEC = 0 through 255 For ATx[7:0]DEC = 0 through 14, the attenuator is set to infinite attenuation. Table 10 lists the attenuation levels for various settings. 28 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): PCM1795 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
