ST7263BEX datasheet(101/186 Pages) STMICROELECTRONICS

101 / 186 page

ST7263Bxx

On-chip peripherals

Doc ID 7516 Rev 8

101/186

Interrupt Status register (ISTR)

Reset value: 0000 0000 (00h)

When an interrupt occurs these bits are set by hardware. Software must read them to

determine the interrupt type and clear them after servicing.

Note:

These bits cannot be set by software.

SUSP

DOVR

CTR

ERR

IOVR

ESUSP

RESET

SOF

Read.write

7 SUSP Suspend mode request.

This bit is set by hardware when a constant idle state is present on the bus line for

more than 3 ms, indicating a suspend mode request from the USB bus. The

suspend request check is active immediately after each USB reset event and its

disabled by hardware when suspend mode is forced (FSUSP bit of CTLR register)

until the end of resume sequence.

6 DOVR DMA over/underrun.

This bit is set by hardware if the ST7 processor can’t answer a DMA request in

time.

0: No over/underrun detected

1: Over/underrun detected

5 CTR Correct Transfer. This bit is set by hardware when a correct transfer operation

is performed. The type of transfer can be determined by looking at bits TP3-TP2 in

EP1-EP0 in register IDR.

0: No Correct Transfer detected

1: Correct Transfer detected

Note: A transfer where the device sent a NAK or STALL handshake is considered

not correct (the host only sends ACK handshakes). A transfer is considered

correct if there are no errors in the PID and CRC fields, if the DATA0/DATA1

PID is sent as expected, if there were no data overruns, bit stuffing or

framing errors.

4 ERR Error.

This bit is set by hardware whenever one of the errors listed below has occurred:

0: No error detected

1: Timeout, CRC, bit stuffing or nonstandard

framing error detected

3 IOVR Interrupt overrun.

This bit is set when hardware tries to set ERR, or SOF before they have been

cleared by software.

0: No overrun detected

1: Overrun detected

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