ST7263BEX datasheet(102/186 Pages) STMICROELECTRONICS

102 / 186 page

On-chip peripherals

ST7263Bxx

102/186

Doc ID 7516 Rev 8

Note:

To avoid spurious clearing of some bits, it is recommended to clear them using a load

instruction where all bits which must not be altered are set, and all bits to be cleared are

reset. Avoid read-modify-write instructions like AND, XOR.

Interrupt Mask register (IMR)

These bits are mask bits for all interrupt condition bits included in the ISTR. Whenever one

of the IMR bits is set, if the corresponding ISTR bit is set, and the I bit in the CC register is

cleared, an interrupt request is generated. For an explanation of each bit, please refer to the

corresponding bit description in ISTR.

Reset value: 0000 0000 (00h)

2 ESUSP End suspend mode.

This bit is set by hardware when, during suspend mode, activity is detected that

wakes the USB interface up from suspend mode.

This interrupt is serviced by a specific vector, in order to wake up the ST7 from Halt

mode.

0: No End Suspend detected

1: End Suspend detected

1 RESET USB reset.

This bit is set by hardware when the USB reset sequence is detected on the bus.

0: No USB reset signal detected

1: USB reset signal detected

Note: The DADDR, EP0RA, EP0RB, EP1RA, EP1RB, EP2RA and EP2RB

registers are reset by a USB reset.

0 SOF Start of frame.

This bit is set by hardware when a low-speed SOF indication (keep-alive strobe) is

seen on the USB bus. It is also issued at the end of a resume sequence.

0: No SOF signal detected

1: SOF signal detected

SUSPM

DOVRM

CTRM

ERRM

IOVRM

ESUSPM

RESETM

SOFM

Read.write

ST7263BEx 数据表(PDF) 102 Page - STMicroelectronics

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