ST7263BEX datasheet(106/186 Pages) STMICROELECTRONICS

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On-chip peripherals

ST7263Bxx

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Doc ID 7516 Rev 8

Endpoint 0 register B (EP0RB)

This register is used for controlling data reception on Endpoint 0. It is also reset by the USB

bus reset.

Reset value: 1000 0000 (80h)

11.4.5

Programming considerations

The interaction between the USB interface and the application program is described below.

Apart from system reset, action is always initiated by the USB interface, driven by one of the

USB events associated with the Interrupt Status register (ISTR) bits.

Initializing the registers

At system reset, the software must initialize all registers to enable the USB interface to

properly generate interrupts and DMA requests.

Initialize the DMAR, IDR, and IMR registers (choice of enabled interrupts, address of

DMA buffers). Refer the paragraph titled initializing the DMA Buffers.

Initialize the EP0RA and EP0RB registers to enable accesses to address 0 and

endpoint 0 to support USB enumeration. Refer to the paragraph titled Endpoint

Initialization.

When addresses are received through this channel, update the content of the DADDR.

If needed, write the endpoint numbers in the EA fields in the EP1RB and EP2RB

Initializing DMA buffers

The DMA buffers are a contiguous zone of memory whose maximum size is 48 bytes. They

can be placed anywhere in the memory space to enable the reception of messages. The 10

most significant bits of the start of this memory area are specified by bits DA15-DA6 in

registers DMAR and IDR, the remaining bits are 0. The memory map is shown in Figure 45.

Each buffer is filled starting from the bottom (last 3 address bits=000) up.

Endpoint Initialization

To be ready to receive, set STAT_RX to VALID (11b) in EP0RB to enable reception.

To be ready to transmit:

Write the data in the DMA transmit buffer.

In register EPnRA, specify the number of bytes to be transmitted in the TBC field

Enable the endpoint by setting the STAT_TX bits to VALID (11b) in EPnRA.

DTOG

STAT

RX1

STAT

RX0

Read.write

7 Forced by hardware to 1.

[6:4] Refer to the EPnRB register for a description of these bits.

[3:0] Forced by hardware to 0.

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